With the industry's seniors chatting, some words let me benefit

1. The difference between master and novice is that the master can use the fewest code to complete the same function, and ensure the least coner, the least bug

2. The function can be correct, then ensure that there is no problem in the synthesis, there are no problems in the following series of processes, the final flow of the film OK. 3.constraints These values are based on the use of the chip environment, measurements or estimates are not given, nor the first parasitic parameters taken out after extraction. Pure by experience. Generally speaking, the CTS produced by the P&r jitter and skew are roughly equivalent to the pre-synthesis estimates, and these things require experience. 4.DCT is the DT Topolo (the back one how to spell, forget). The specific is similar to the physical synthesis, the front-end integration into place of the def. Methodological, or DC direct support is only a difference in the process. Promot is the case. There are some in UG. 5.hierarchy deep does not matter, as long as r2r between the logic depth is not deep, that synthesis will not have the problem. Hier deep, no effect on synthesis unless you use bottom-up synthesis, and the logical hierarchy is not optimized otherwise. When we write a detailed plan, we consider that under the process of use, the maximum logical depth in a given constraint, and then consider the logic depth can not be too deep 6.top level directly integrated, can get the best results. Generally only the chip is too big, can not top direct synthesis, only take subchip alone synthesis, top on only link method (top no other logic). Because the big project is subchip alone synthesis, top on the synthesis, top synthesis when the subchip if far away, the delay of the connection is i->reg input delay. 7. Master, all of the process library very well know about each and,or, The delay of the MUX is how large. 8. As the basic skills of the designer, do not always with DC, strengthen their understanding of the circuit, there are some very common agreement and so on, is the most important. 9. Commonly used module design, the most efficient, the most not waste is, the design of common circuit. The IC class interview, the written test, all only ask this. After work, it's important to get a good look at the tools. Take a look at the previous agreement ah, this is the third step, but also depends on your future company to do something. 10. Because there are many very experienced people, will process their experience, to ensure that the process is the most reliable newcomer only need to run, the design task is not to run DC, but according to the requirements of the design of the most optimized circuit. In a project, there will be a lot of things to run the process to do, at that time, what to learn what to do, in school, if you see more, see more, or have contact, in use, will Get started a lot faster 11. The difference between master and novice is that the master can use the fewest code to complete the same function, and ensure the least coner, the least bug, the readability is very high. Often the novice writes the RTL is obscure difficultUnderstand and master some are very indirect. Is something that is not easy to happen and verified, but those situations can lead to problems with your design.  

Chat with the industry's seniors, some words to my benefit