I have been reading this item during this time. Today I will summarize it:
To understand the real and protection modes, let's talk about the history of intel X86 CPU development.
Starting from 8086, 8086 is a 16-bit CPU (why is it a 16-bit address line? No, because 8086 is a 20-bit address line, which generally refers to the width of the "arithmetic logic unit" ALU In the processor. The data section in the system bus, known as the "Data Bus", usually
the ALU unit in the chip.
The multi-level cache design is used to hide latency (the spatial and temporal locality principles can be well utilized)
The limited number of registers makes it possible to have too many active threads at the same time.
Control the execution of the logical unit recording program, provide the instruction set parallelism (ILP), and minimize the vacant cycle of the CPU pipeline (STLs, at which the
Since the invention of the transistor in human 1947span> years, more than 50 years of semiconductor technology experienced silicon transistors, integrated circuits, VLSI, very large scale integrated circuits and other generations, the rapid development of other industries are not. Semiconductor technology has a wide impact on society as a whole, so it is called "the seed of industry". CPU refers to the computer internal data processing and control of the processing process of the parts, with the
1.3 Basic components and working principles of computers
Basic Components of hardware: memory, controller, memory, input device, and output device
The memory and controller have been integrated into the CPU
ALU is a component used to process data. It can complete both arithmetic operations and logical operations. Therefore, it is called an arithmetic logic component.
Controller: The main function is to extract and analyze commands from the master memo
into the Tgsi intermediate language, and then the graphics card specific driver compiles the Tgsi language code into GPU instructions, which is shown in 1 (regardless of geometry shader and tesselation shader). Here is a detailed description of the TGSI. This master's thesis, "Advanced coloring Language and its optimized compilation", has a more detailed discussion on GLSL and low-level coloring languages.2 R600 InstructionsPrograms running on the CPU, all the fetch instructions and operation i
related to hardware, making it difficult to understand the computer principle or architecture, it is hard to learn the assembly. This also makes many people far away from the assembly, because it is too lazy to learn the assembly to learn computer principles. However, the assembly is such an important language, to learn it, not necessarily to use it, at least you can better understand the computer system and software implementation of the bottom. A senior in CS Field said: All CS problems can b
problem arises, the Alu width is only 16 bits, that is, the ALU can not calculate the 20-bit address. In order to solve this problem, the segmentation mechanism was introduced and boarded the historical stage.To support fragmentation, the 8086 processor has four segment registers: CS, DS, SS, ES. Each segment register is 16 bits, and the address in the instruction that accesses the memory is also 16 bits.
1.10101, the index is 2, so the order is 2+127=129 (plus 127 is the stipulation);So-6.625 IEEE floating-point numbers are represented as:
1 10000001 10101000000000000000000
(3) The operation of the numberPreviously said with the complement to calculate relatively simple, it is time to reveal the answer.Let's take a look at the arithmetic of integers first.The operation of integers is performed with the complement.The addition of the complement is also very simple, as with decimal addition, if a
instruction is decoded to finally find the data stored in the register required by the instruction. If the instruction is only a jump instruction, then at this stage you need to compare the obtained value according to the meaning of the jump instruction, if the comparison result is true then the jump is performed, if the comparison result is false, the jump is not performed, and the next instruction is executed if the instruction needs to fill some bits in the instruction. It is also done in th
.
⑥ Undefined command exception mode: This mode is entered when undefined commands are executed. It is mainly used to handle undefined command traps and supports software simulation of hardware coprocessor, because undefined commands mostly occur in coprocessor operations.
7. System Mode: uses the privileged mode of the same register group as the user mode to run privileged operating system tasks.
Difference: privileged mode-a program can access all system resources or switch the processor mode
Dhs4002, the first shot. I bought it in the last semester. I am so sorry to use my deskmate. I have bought it for months, and I am working with pf4 on both sides. The skin on both sides of the interface ages up and then changes to 729 and 729-2, and then to the Palio overhead and Palio cj8000.
Stiga tube alu fl, my first professional background, was fooled by the Moderator of a professional forum. This Board is not suitable for me at all. The product
System hardware
CPU-Central processing unit
Alu-Arithmetic logic unit
PC-Program counter
USB-Universal Serial Bus
BusBus, a group of electronic pipelines throughout the system, passing byte-stream information between the various components.A block of bytes, called a word, that transmits a fixed length, the number of bytes in a word, called the length of words.ProcessorCPU, central processing unit, is the engine that interpret
-processing units are equivalent to AMD's 5 flow-processing units (as development may vary).
The streaming processor directly maps the multimedia graphics data stream to the stream processor for processing, which is programmable and not programmable. The bandwidth between the stream memory and the SRF is the bandwidth between the 2GB/S,SRF and the processor registers is 32gb/s,alu Cluster (ALU cluster) The
awkward problem arises, the ALU is only 16 digits wide, that is, the ALU can not calculate the 20-bit address. In order to solve this problem, the segmented mechanism was introduced and boarded the stage of history.
To support fragmentation, the 8086 processor is set up with four segment registers: Cs,ds,ss, ES. Each segment register is 16 bits, and the address in the instruction that accesses the memory i
programmers do not agree ). In intel optimization referfence manual, special advantages of this command are mentioned.
0. The LEA command has a single clock cycle, and the execution efficiency is very high.
1. It is the CPU address generation unit involved in the operation, rather than ALU involved in the operation, so it will not be related to the flow of contextual Arithmetic Logic commands;
Lea is not executed in
Label: style Io OS use SP data on log CTI
1. Which three subsystems do computers consist?
CPU, primary storage, and input/output subsystems.
2. What components does the CPU consist?
Arithmetic logical unit (ALU), control unit and a series of registers.
3. What are ALU functions?
The arithmetic logical unit is responsible for arithmetic, shift, and logical operations.
4. What are the functions
requires three main components: the combination logic that computes the function that operates on the bit, the memory element that stores the bits, and the clock signal that controls the update of the memory element.
And, or, not three kinds of logic gates can be implemented with a gate (with a non-gate, or not gate).
Multiplexer. The multiplexer selects one from a different set of data signals based on the value of the input control signal.
The ALU
Position + 8;
The other pipelines are analogous here.Ii. Arm Assembly Line Overview
IntroductionPipeline technology shortens program execution time and improves the efficiency and throughput of the processor core by running multiple functional components in parallel, thus becoming one of the most important technologies in microprocessor design. The ARM7 processor core uses a typical three-level assembly line structure of Feng nuiman, while the arm9-series uses a five-level assembly line structu
Introduction Pipeline Technology is shortened by parallel work of Multiple Functional Components Program The execution time improves the efficiency and throughput of the processor core, thus becoming one of the most important technologies in the design of the microprocessor. The ARM7 processor core uses a typical three-level assembly line of Feng nuiman, while the arm9-series uses a five-level assembly line of the Harvard structure. The logic at all levels of the assembly line is simplified by i
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