ddr1 sdram

/compressed/head-s3c2410.S** Copyright (c) 2002 Samsung Electronics Sw. Lee **/@The SDRAM on my Development Board is: HY57V561620FTP-H, 4mx16bitx4banks, two pieces are connected to 32bit, 64 MB, connected to bank6, the address range is: [0x30000000-0x33ffffff]@ (I haven't figured out the structure of the SDRAM. Why do I need to divide it into banks? I'll take a look at the relevant documents in another day)

language are called during initialization ). As follows: @*************************************** *************************************** @ File: head. s @ Function: Set the SDRAM, copy the program to the SDRAM, and then jump to the SDRAM to continue execution. @*************************************** *************************************** . Extern main . Tex

. [System suspend status] When you press the off button or the application calls the API to enter the suspend state, the kernel calls the oempoweroff () function. the system is suspended in the oempoweroff () function. After the system is awakened, it continues to be executed from where oempoweroff () is suspended. when oempoweroff () is enabled, the sleep mode is selected based on the sleep mode of the CPU chip and the lowest power consumption mode is selected. if the lowest power consumption m

set to 1 and then enters (3) power-down mode (Power_OFF) CLKCON [3] is set to 1 III. preparations before S3C2410 enters the power-down mode 1. set reasonable GPIO for power-down mode 2. Block all interrupts in the interrupt shield register. 3. reasonably configure the wake-up source, including real-time clock 4. suspend USB. Miscr [] = 11b 5. store the sleep return address or data that is not lost in the power-down mode in GSTATUS3, 4 6. configure miscr [1:0] to pull the data bus 7. disable LC

I. Causes and principlesCause: In the past computer burning write bootloader to NAND is using JTAG and Jflash,jtag is connected with the port, the current computer is generally not the same mouth, now generally used cheaper to start the J-link, using USB, you can no longer use the previous Jflash burned write. It is therefore necessary to find a way to J-link write NAND. The following instructions j-link the principle of burning nand. With the realarm2410 Development Board as an example, the Dev

1.1 embedded processor s3c2440a [17] S3c2440a is a dedicated chip designed mainly for handheld devices. It features low power consumption and high-speed processing and computing capabilities. To reduce system consumption, 2440 uses the following components: 2440 Based on the ARM920T kernel, 0.13um CMOS standard unit and storage unit complex, its power consumption and small, simple, and stable design are very suitable for products with high power requirements. S3c2440a adopts the ARM920T kernel a

the tag_header structure that identifies the passed parameter and the subsequent parameter value data structure. The data structure tag and tag_header are defined in the include/ASM/setup. h header file of the Linux kernel source code. In Embedded Linux systems, the following common startup parameters are required by Bootloader: atag_core, atag_mem, atag_cmdline, atag_ramdisk, and atag_initrd. (Note) parameters can also be set using CommandLine. In my bootloader, I use both of them. 2. Developm

the kernel through the startup parameter. for more information, see code analysis.Startup parameters (from IBM Developer)Before calling the kernel, make one step of preparation, that is, set the Linux kernel startup parameters. Linux 2.4.x and later kernels all expect to pass startup parameters in the form of tagged list. Start the parameter tag list to mark atag_core and end with atag_none. Each tag consists of the tag_header structure that identifies the passed parameter and the subsequent pa

We all know that U-BOOT is divided into two stages. The first stage is (~ /Cpu/arm920t/start. in seconds) run on FLASH (generally) to initialize the hardware, including the watchdog and cache interruption, in addition, it is responsible for moving the code to the SDRAM (checking whether the code is in the SDRAM during the migration), and then completing the establishment of the environment required for the

Objective: To enable MMU, map the address space of the SDRAM, and operate the virtual address to implement the "lighting method" to master the usage of MMU. Tutorial environment and Description: h2410, hengyi S3C2410 Development Board. The h2410 core board is extended with 64 MB k4s561632 SDRAM (4 M * 16bit * 4 bank). The address range is 0x30000000 ~ 0x33ffffff. The IP address range of the gpio port is 0x5

AbstractIn early August, I was going to go to Youjing technology to get a chance to connect to the Youjing engineering site. If there is any de2 suspected zookeeper, I can ask you on behalf of me. IntroductionI will go to Youjing in early August: the hardware design and practice of the machine's Virtual Machine [2008/8/3, 8/10, 8/17]. I have the chance to meet Youjing's engineering workshop, if you have any questions in de2, you are welcome to leave a message in this post. I can ask you for he

correct driver for the new adapter. (2). chipset features setup1. SDRAM Ras-to-cas delay (SDRAM RAS-CAS delay) Option: 2, 3This option allows you to set the delay time for the RAS-CAS. When set to 2, the latency of the SDRAM memory can be reduced to improve the speed of memory read/write. If the system is unstable after it is set to 2, it can be restored to the

Rom and RAM are both semiconductor memory, Rom is short for read only memory, and Ram is short for random access memory. ROM can still maintain data when the system stops power supply, while Ram usually loses data after power loss. A typical Ram is the computer memory.Ram has two categories: static RAM (static RAM/SRAM). The speed of SRAM is very fast. It is the fastest storage device for reading and writing, but it is also very expensive, so it is only used in demanding places, such as the firs

Reprint: http://blog.csdn.net/xxblinux/article/details/6281295We all know that U-boot is divided into two stages, the first stage is (~/cpu/arm920t/start). s) run on Flash (in general), complete the initialization of the hardware, including the watchdog, interrupt cache, etc., and is responsible for moving the code into the SDRAM (when moving to check if their code is in SDRAM), and then complete the C prog

Http://hi.baidu.com/lisuo/blog/item/9495940afd213e1794ca6b7d.html Http://forum.eet-cn.com/FORUM_POST_10012_1200027579_0.HTM Memory interface types can be divided: Asynchronous memory interface and synchronous storage interface.Asynchronous memory interface type is the most common and well-known. Generally, MCU This type of interface is used. Corresponding memory: SRAM, Flash, NVRAM ...... And many other Analog/digital I/O devices connected in parallel, such as A/D, D/A, and open-in/Ope

translate the address to be accessed in an instruction into a physical address, which is then sent to the bus process. There is a book called Understand Linux kernel, patience to see, that book is very good writing.The MMU is the product of a complex processor to a certain extent. This thing and operating system memory management if combined to learn and understand, the best effect.Embedded system, the storage system is very different, can contain many types of storage devices, such as Flash,sr

Previous chores more, did not study carefully, this semester as far as possible to use free time to learn to understand.@*************************************************************************@ Set the SDRAM, copy the program to SDRAM, Then jump to SDRAM and continue with the @ -. One.8by huangtao@****************************************************************

SDRAM according to the image Macro Block (such as 8x8 pixel MCU block). The second solution is to add a FIFO buffer, and the image data is stored directly by the DMA controller, this scheme can save the software overhead of niosⅱ and complete image acquisition more efficiently.The FPGA used in this system is the EP1C6Q240C8 of Altera. It has 5980 LC (logic gate unit) and 20 M4K RAM blocks. An 11-bit deep DMA controller designed in this system require

address or data that is not lost in the power-down mode in GSTATUS3, 4 6. Configure miscr [1:0] to pull the data bus 7. Disable LCD 8. Read REFRESH, CLKCON, and miscr registers to populate TLB. 8th points may be a little difficult to understand. You need to explain it: The reason is that you need to suspend the SDRAM before entering the power-down mode. After the SDRAM is suspended, you also need to operat

Address: http://www.cnblogs.com/oomusou/archive/2008/11/20/sopc_byteenable.html AbstractWhen developing a mater IP address, we can determine the degree of parallelism of the data bus, or determine which bytes are valid through byteenable. But are these two methods the same? IntroductionWhy is there such a demand first? The reason is that the cpu Of the nio ii is 32 bit, so if all IP addresses are 32 bit, the world is peaceful, everything is everything,Because the data bus of the